philips semiconductors product specification powermos transistor BUK107-50DS logic level topfet description quick reference data monolithic overload protected logic symbol parameter max. unit level power mosfet in a surface mount plastic envelope, intended as v ds continuous drain source voltage 50 v a general purpose switch for automotive systems and other i d continuous drain current 0.7 a applications. p d total power dissipation 1.8 w applications t j continuous junction temperature 150 ?c general controller for driving lamps r ds(on) drain-source on-state resistance 175 m w small motors solenoids features functional block diagram vertical power dmos output stage overload protected up to 85?c ambient overload protection by current limiting and overtemperature sensing latched overload protection reset by input input clamping suitable for pull-up resistor drive circuit control of power mosfet and supply of overload protection circuits derived from input esd protection on all pins overvoltage clamping for turn off of inductive loads fig.1. elements of the topfet. pinning - sot223 pin configuration symbol pin description 1 input 2 drain 3 source 4 drain (tab) power mosfet drain source input o/v clamp logic and protection rig 4 1 23 p d s i topfet march 1997 1 rev 1.200
philips semiconductors product specification powermos transistor BUK107-50DS logic level topfet limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v ds continuous drain source voltage 1 - - 50 v i d continuous drain current 2 - - self limiting a i i continuous input current clamping - 3 ma i irm non-repetitive peak input current t p 1 ms - 10 ma p d total power dissipation t amb = 25 ?c - 1.8 w t stg storage temperature - -55 150 ?c t j continuous junction temperature normal operation 3 - 150 ?c esd limiting value symbol parameter conditions min. max. unit v c electrostatic discharge capacitor human body model; - 2 kv voltage c = 250 pf; r = 1.5 k w overvoltage clamping limiting values at a drain source voltage above 50 v the power mosfet is actively turned on to clamp overvoltage transients. symbol parameter conditions min. max. unit e dsm non-repetitive clamping energy t b 25 ?c; i dm < i d(lim) ; - 100 mj inductive load e drm repetitive clamping energy t b 75 ?c; i dm = 50 ma; - 4 mj f = 250 hz overload protection limiting values with the protection supply provided via the input pin, topfet can protect itself from short circuit loads. overload protection operates by means of drain current limiting and activating the overtemperature protection. symbol parameter conditions min. max. unit v ddp protected drain source supply voltage i i = 1.5 ma - 35 v v is = 6 v - 16 v overload protection characteristics topfet switches off to protect itself when there is an overload fault condition. it remains latched off until reset by the input. symbol parameter conditions min. typ. max. unit overload protection i d(lim) drain current limiting i i = 1.5 ma 0.7 1.1 1.5 a overtemperature protection only in drain current limiting t j(to) threshold junction temperature i i = 1.5 ma 100 130 160 ?c 1 prior to the onset of overvoltage clamping. for voltages above this value, safe operation is limited by the overvoltage clampi ng energy. 2 refer to overload protection characteristics. 3 not in an overload condition with drain current limiting. march 1997 2 rev 1.200
philips semiconductors product specification powermos transistor BUK107-50DS logic level topfet thermal characteristics symbol parameter conditions min. typ. max. unit thermal resistance r th j-sp junction to solder point - 12 18 k/w r th j-b junction to board 1 mounted on any pcb - 40 - k/w r th j-a junction to ambient mounted on pcb of fig. 19 - - 70 k/w static characteristics t b = 25 ?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (cl)dss drain-source clamping voltage v is = 0 v; i d = 10 ma 50 55 - v v (cl)dss drain-source clamping voltage v is = 0 v; i dm = 200 ma; - 56 70 v t p 300 m s; d 0.01 i dss off-state drain current v ds = 45 v; v is = 0 v - 0.5 2 m a i dss off-state drain current v ds = 50 v; v is = 0 v - 1 20 m a i dss off-state drain current v ds = 40 v; v is = 0 v; t j = 100 ?c - 10 100 m a r ds(on) drain-source on-state i i = 1.5 ma; i dm = 100 ma; - 125 175 m w resistance 2 t p 300 m s; d 0.01 input characteristics t b = 25 ?c unless otherwise specified. the supply for the logic and overload protection is taken from the input. the input clamping is suitable for a drive circuit with a pull-up resistor. symbol parameter conditions min. typ. max. unit v is(to) input threshold voltage v ds = 5 v; i d = 1 ma 1.7 2.2 2.7 v i is input supply current normal operation; v is = 6 v - 550 750 m a i isl input supply current protection latched; v is = 5 v - 500 650 m a v is = 3.5 v - 250 400 m a v isr protection latch reset voltage 3 1 2.2 3.5 v v (cl)is input clamping voltage i i = 1.5 ma 6 7.5 - v r ig input series resistance to gate of power mosfet - 33 - k w switching characteristics t amb = 25 ?c; resistive load r l = 50 w ; adjust v dd to obtain i d = 250 ma; refer to test circuit and waveforms symbol parameter conditions min. typ. max. unit t d on turn-on delay time v is = 0 v to i i = 1.5 ma - 4 - m s t r rise time - 16 - m s t d off turn-off delay time i i = 1.5 ma to v is = 0 v - 3 - m s t f fall time - 6 - m s 1 temperature measured 1.3 mm from tab. 2 continuous input voltage. the specified pulse width is for the drain current. 3 the input voltage below which the overload protection circuits will be reset. march 1997 3 rev 1.200
philips semiconductors product specification powermos transistor BUK107-50DS logic level topfet fig.2. normalised limiting power dissipation. p d % = 100 p d /p d (25 ?c) = f(t mb ) fig.3. continuous drain current. i d = f(t amb ); condition: i i = 1.5 ma fig.4. typical on-state characteristics, t j = 25 ?c. i d = f(v ds ); parameter v is ; t p = 300 m s fig.5. normalised drain-source on-state resistance. a = r ds(on) /r ds(on) 25 ?c = f(t j ); i d = 100 ma; i i = 1.5 ma fig.6. typical on-state resistance, t j = 25 ?c. r ds(on) = f(v is ); conditions: i d = 100 ma, t p = 300 m s fig.7. typical transfer characteristics, t j = 25 ?c. i d = f(v is ); conditions: v ds = 10 v, t p = 300 m s 0 20 40 60 80 100 120 140 tmb / c pd% normalised power derating 120 110 100 90 80 70 60 50 40 30 20 10 0 -60 -40 -20 0 20 40 60 80 100 120 140 tj / c a normalised rds(on) = f(tj) 1.5 1.0 0.5 0 0 20 40 60 80 100 120 140 tamb / c id / a BUK107-50DS 2.0 1.5 1.0 0.5 0 within the shaded region current limiting occurs typ. 0 2 4 6 8 10 vis / v rds(on) / mohm BUK107-50DS 240 200 160 120 80 40 0 typ. 0 4 8 12 16 20 24 28 32 vds / v id / a BUK107-50DS 1.5 1 0.5 0 vis / v = 5 6 7 8 0 2 4 6 8 10 vis / v id / a BUK107-50DS 1.5 1 0.5 0 march 1997 4 rev 1.200
philips semiconductors product specification powermos transistor BUK107-50DS logic level topfet fig.8. typical overtemperature protection threshold. t j(to) = f(v is ); condition: v ds = 10 v fig.9. typical dc input characteristics, t j = 25 ?c. i is & i isl = f(v is ); normal operation & protection latched fig.10. typical dc input current. i is = f(t j ); parameter v is ; normal operation fig.11. input threshold voltage. v is(to) = f(t j ); conditions: i d = 1 ma; v ds = 5 v fig.12. typical input clamping characteristic. i i = f(v is ); normal operation, t j = 25 ?c. fig.13. overvoltage clamping characteristic, 25 ?c. i d = f(v ds ); conditions: v is = 0 v; t p 300 m s 0 2 4 6 8 10 vis / v tj(to) / c BUK107-50DS 200 180 160 140 120 100 80 60 typ. -50 0 50 150 tj / c vis(to) / v BUK107-50DS 3 2 1 typ. max. min. 100 0 2 4 6 8 vis / v iis & iisl / ma BUK107-50DS 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 iisl iis reset normal latched 0 2 4 6 8 10 vis / v ii / ma BUK107-50DS 10 9 8 7 6 5 4 3 2 1 0 -50 50 150 tj / c iis / ua BUK107-50DS 500 400 300 200 100 0 100 0 5 v 4 v vis / v = 50 52 54 56 58 60 vds / v id / ma BUK107-50DS 200 150 100 50 0 typ. march 1997 5 rev 1.200
philips semiconductors product specification powermos transistor BUK107-50DS logic level topfet fig.14. test circuit for resistive load switching times. select r i to give i i = 1.5 ma, ie 3.3 k w approx. fig.15. typical switching waveforms, resistive load . r l = 50 w ; adjust v dd to obtain i d = 250 ma; t j = 25?c fig.16. typical drain source leakage current i dss = f(t j ); conditions: v ds = 40 v; v is = 0 v. vdd d.u.t. 0v d s i topfet p rl vds measure ri 10 ko bc337 vis -50 50 150 tj / c idss BUK107-50DS 10 ua 1 ua 100 na 10 na 100 0 -10 10 30 50 70 90 time / us vis & vds / v BUK107-50DS 15 10 5 0 vis vds fig.17. transient thermal impedance, topfet mounted on pcb of fig 19. z th j-amb = f(t); parameter d = t p /t 0.5 0.2 0.1 0.05 0.02 1e-07 1e-05 1e-03 1e-01 1e+01 1e+03 t / s zth j-amb / (k/w) 1e+02 1e+01 1e+00 1e-01 1e-02 0 BUK107-50DS d = t p t p t t p t d d = march 1997 6 rev 1.200
philips semiconductors product specification powermos transistor BUK107-50DS logic level topfet mounting instructions dimensions in mm. fig.18. soldering pattern for surface mounting. printed circuit board dimensions in mm. fig.19. pcb for thermal resistance and power rating. pcb: fr4 epoxy glass (1.6 mm thick), copper laminate (35 m m thick). 36 60 9 10 4.6 18 4.5 7 15 50 3.8 min 6.3 2.3 4.6 1.5 min 1.5 min 1.5 min (3x) march 1997 7 rev 1.200
philips semiconductors product specification powermos transistor BUK107-50DS logic level topfet mechanical data dimensions in mm net mass: 0.11 g fig.20. sot223 surface mounting package 1 . handbook, full pagewidth 6.7 6.3 0.95 0.85 2.3 0.80 0.60 4.6 3.1 2.9 3.7 3.3 7.3 6.7 a b 0.2 a 1.80 max 16 16 o max 10 o max 0.10 0.01 0.32 0.24 4 123 msa035 - 1 (4x) 0.1 b m m s seating plane 0.1 s o 1 for further information, refer to surface mounting instructions for sot223 envelope. epoxy meets ul94 v0 at 1/8". march 1997 8 rev 1.200
philips semiconductors product specification powermos transistor BUK107-50DS logic level topfet definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1997 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. march 1997 9 rev 1.200
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